The present invention relates to semiconductor packages, and more particularly, to a multi-chip semiconductor package mounted with stacked chips therein.
Stack semiconductor packages are advanced packaging technology, which is characterized by stacking a plurality of chips in a single package structure, so as to desirably multiply operational performances and memory capacity for semiconductor packages.
Conventional chip-stack structures are exemplified with reference to FIGS. 5A to 5C. As shown in FIG. 5A, two chips 10, 11 are stacked on a substrate 12, and electrically connected to the substrate 12 by means of bonding wires 13, 14 respectively. Such a structure is limited to a relatively smaller size of the overlying chip 11 with respect to the underlying chip 10, whereby forming of the bonding wires 13 would not be interfered by stacked arrangement of the chips 10, 11.
A solution to chip-size limitation, as shown in FIG. 5B, is to apply an adhesive 15 between the two chips 10, 11 in a manner that, the adhesive 15 is sufficiently dimensioned in thickness for allowing the overlying chip 11 to be mounted on the underlying chip 10 without coming into contact with the bonding wires 13, such that the overlying chip 11 can be sized equally or even larger in surface area than the underlying chip 10.
Alternatively, as shown in FIG. 5C, the adhesive 15 can further spread to cover wire loops 130 of the bonding wires 13 received between the chips 10, 11. Such a structure provides significant benefits. First, the bonding wires 13 can be firmly assured without being interfered by the chip-stack arrangement. Moreover, the wire loops 130 are held in position within the adhesive 15, and thereby the bonding wires 13 would be less likely to suffer wire sagging or sweep due to strong mold-flow impact of a molding compound or resin for forming a chip-enclosed encapsulant (not shown) during a molding process. Wire sagging or sweep would cause electrical contact or short circuit between adjacent bonding wires or between bonding wires and chips, thereby undesirably damaging electrical quality and yield for fabricated products.
However, the above conventional chip-stack structures are primarily used to accommodate chips with peripherally-situated bond pads where bonding wires are bonded, but not suitably applied for stacking chips with centrally-situated bond pads such as DRAM (dynamic random access memory) chips. For example, in the chip-stack structures of FIGS. 5A and 5B, if the underlying chip 10 is formed with centrally-situated bond pads, either the overlying chip 11 (FIG. 5A) or the adhesive 15 (FIG. 5B) would undesirably cover the bond pads, thereby making bonding wires 13 not possibly connected to the bond pads for electrically connecting the underlying chip 10 to the substrate 12.
For the chip-stack structure illustrated in FIG. 5C, wire loops 130 of the bonding wires 13 (bonded to peripherally-situated bond pads 16) are encapsulated by the adhesive 15. If bond pads 16 formed on the underlying chip 10 are adapted to be centrally situated, the wire loops 130 extending from centrally-situated bond pads would need to be made with a considerable height, so as to prevent the bonding wires 13 from coming into contact with edge of the underlying chip 10. As a result, the adhesive 15 correspondingly needs to increase in thickness for accommodating the enlarged wire loops 130, for the purposes of positioning the bonding wires 13 and preventing short circuit or wire sweep from occurrence. Such structural arrangement would greatly increase overall package profile, thereby not applicable in practical use or fabrication for semiconductor packages.
Therefore, it is highly desired to develop a semiconductor package for stacking chips with centrally-situated bond pads, by which package profile can be desirably miniaturized as well as electrical quality can be firmly assured.
an objective of the present invention is to provide a low profile stack semiconductor package for use to stack chips having centrally-situated bond pads, such as DRAM (dynamic random access memory) chips, in a face-up (active surface up) manner.
Another objective of the invention is to provide a low profile stack semiconductor package, which can effectively reduce size or profile of overall package structure.
A further objective of the invention is to provide a low profile stack semiconductor package, which can significantly maintain electrical quality thereof, and prevent short circuit or wire sweep from occurrence.
A further objective of the invention is to provide a low profile stack semiconductor package, which can desirably reduce pitch spacing between adjacent bonding wires, allowing the semiconductor package to be suitably applied to high-level products with fine-pitch structural arrangement.
In accordance with the above and other objectives, the present invention proposes a low profile stack semiconductor package, comprising: a substrate; a lower chip having an active surface formed with a plurality of centrally-situated bond pads thereon, and a non-active surface opposed to the active surface, wherein the non-active surface is mounted on the substrate, and a cushion member is formed at a peripheral edge on the active surface of the lower chip; a plurality of bonding wires for electrically connecting the lower chip to the substrate in a manner that, the bonding wires extend from the bond pads of the lower chip in a direction substantially parallel to the active surface of the lower chip, and reach the cushion member beyond which the bonding wires turn to be directed toward the substrate, wherein the bonding wires are free of forming wire loops as extending above the active surface of the lower chip, and the cushion member is interposed between the bonding wires and the lower chip, allowing the bonding wires to be free of contact with the lower chip; an adhesive applied over the active surface of the lower chip in a manner as to encapsulate the bond pads, the cushion member and part of the bonding wires extending above the lower chip; an upper chip having an active surface and a non-active surface opposed to the active surface, wherein the non-active surface is mounted on the adhesive, and the active surface is electrically connected to the substrate; an encapsulant for encapsulating the lower and upper chips, and the bonding wires; and a plurality of solder balls implanted on the substrate and exposed to outside of the encapsulant, for electrically connecting the lower and upper chip to an external device.
By the above package structure, chips having centrally-situated bond pads, such as DRAM chips, can be easily stacked on a substrate in a face-up (active surface up) manner through the use of an adhesive as an interposer between adjacent vertically stacked chips. Bonding wires for electrically connecting a chip to the substrate, extend from centrally-situated bond pads of the chip in a direction substantially parallel to the chip, without forming wire loops above the chip. Therefore, when applying the adhesive over the chip, the adhesive can be made considerably thin for sufficiently encapsulating the bonding wires. This allows the chip to be readily stacked with another chip thereon. By virtue of the adhesive forming a protection layer on an underlying chip, stacking of an overlying chip over the underlying chip would not affect or damage structural or electrical arrangement (e.g. bonding wires) formed on the underlying chip.
A cushion member peripherally formed on a chip, is used to space bonding wires apart from the chip, by which undesirable contact or short circuit between the bonding wires and chip can be prevented from occurrence. The cushion member is preferably made of an elastic or semi-cured insulating material. Thereby, when bonding wires come into contact with the cushion member, each of the bonding wires would be partly embedded in the cushion member. Further with the adhesive being applied over the bonding wires, the bonding wires can be firmly held in position and properly spaced apart from each other as being interposed between the adhesive and cushion member, without causing wire sagging or sweep that leads to short circuit or adversely damages electrical quality of fabricated packages. Therefore, bonding wires can be more densely or closely arranged in a manner as to reduce pitch spacing between adjacent bonding wires, making the package structure suitably applied to high-level products with fine-pitch structural arrangement.